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GS841E18AT/B-180/166/150/130/100
TQFP, BGA Commercial Temp Industrial Temp Features
* 3.3 V +10%/-5% core power supply, 2.5 V or 3.3 V I/O supply * Dual Cycle Deselect (DCD) * Intergrated data comparator for Tag RAM application * FT mode pin for flow through or pipeline operation * LBO pin for Linear or Interleave (PentiumTM and X86) Burst mode * Synchronous address, data I/O, and control inputs * Synchronous Data Enable (DE) * Asynchronous Output Enable (OE) * Asynchronous Match Output Enable (MOE) * Byte Write (BWE) and Global Write (GW) operation * Three chip enable signals for easy depth expansion * Internal self-timed write cycle * JTAG Test mode conforms to IEEE standard 1149.1 * JEDEC-standard 100-lead TQFP package and 119-BGA * Pb-Free 100-lead TQFP package available
256K x 18 Sync Cache Tag
180 MHz-100 MHz 3.3 V VDD 3.3 V and 2.5 V I/O
Output registers and the Match output register are provided and controlled by the FT mode pin (Pin 14). Through use of the FT mode pin, I/O registers can be programmed to perform pipeline or flow through operation. Flow Through mode reduces latency. Byte write operation is performed by using Byte Write Enable (BWE) input combined with two individual byte write signals BW1-2. In addition, Global Write (GW) is available for writing all bytes at one time. Compare cycles begin as a read cycle with output disabled so that compare data can be loaded into the data input register. The comparator compares the read data with the registered input data and a match signal is generated. The match output can be either in Pipeline or Flow Through modes controlled by the FT signal. Low power (Standby mode) is attained through the assertion of the ZZ signal, or by stopping the clock (CLK). Memory data is retained during Standby mode. JTAG boundary scan interface is provided using IEEE standard 1149.1 protocol. Four pins--Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS)--are used to perform JTAG function. The GS841E18A operates on a 3.3 V power supply and all inputs/ outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output (VDDQ) pins are used to allow both 3.3 V or 2.5 V IO interface.
Functional Description
The GS841E18A is a 256K x 18 high performance synchronous DCD SRAM with integrated Tag RAM comparator. A 2-bit burst counter is included to provide burst interface with PentiumTM and other high performance CPUs. It is designed to be used as a Cache Tag SRAM, as well as data SRAM. Addresses, data IOs, match output, chip enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC, ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are synchronous and are controlled by a positive-edge-triggered clock (CLK). Output Enable (OE), Match Output Enable, and power down control (ZZ) are asynchronous. Burst can be initiated with either ADSP or ADSC inputs. Subsequent burst addresses are generated internally and are controlled by ADV. The burst sequence is either interleave order (PentiumTM or x86) or linear order, and is controlled by LBO.
Dual Cycle Deselect (DCD)
The GS841E18A is a DCD pipelines synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD SRAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of the clock.
Parameter Synopsis
-180 Pipeline 3-1-1-1 Flow Through 2-1-1-1 tcycle tKQ IDD tKQ tcycle IDD 5.5 ns 3.2 ns 335 mA 8 ns 9.1 ns 210 mA -166 6.0 ns 3.5 ns 310 mA 8.5 ns 10 ns 190 mA -150 6.6 ns 3.8 ns 275 mA 10 ns 10 ns 190 mA -133 7.5 ns 4.0 ns 250 mA 11 ns 15 ns 140 mA -100 10 ns 4.5 ns 190 mA 12 ns 15 ns 140 mA
Rev: 1.03 4/2005
1/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. * Pentium is a trademark of Intel
GS841E18AT/B-180/166/150/130/100
Pin Configuration (Package T)
VDDQ VSS NC NC D DQ VSS VDDQ DQ DQ FT VDD NC VSS DQ DQ VDDQ VSS DQ DQ DQP NC VSS VDDQ NC NC NC
NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A CE1 CE2 NC NC BW2 BW1 CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
A NC NC VDDQ VSS NC DQP DQ DQ VSS VDDQ DQ DQ VSS NC VDD ZZ DQ DQ VDDQ VSS DQ DQ NC NC VSS VDDQ
MATCH
DE MOE
Rev: 1.03 4/2005
LBO A A A A A1 A0 TMS TDI VSS VDD TDO TCK A A A A A A A 2/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
GS841E18A PadOut--119-Bump BGA--Top View (Package B)
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC VDDQ
2
A E2 A NC DQB NC DQB NC VDD DQB NC DQB NC DQP
A
3
A A A VSS VSS VSS BB VSS NC VSS NC VSS VSS VSS LBO A TDI
4
ADSP ADSC VDD NC E1 G ADV GW VDD CK NC BW A1 A0 VDD NC TCK
5
A A A VSS VSS VSS NC VSS NC VSS BA VSS VSS VSS FT A TDO
6
A E3 A DQP NC DQA NC DQA VDD NC DQA MATCH DQA MOE A A NC
7
VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ DE DQA NC ZZ VDDQ
A TMS
Rev: 1.03 4/2005
3/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
TQFP Pin Description Symbol
An CLK BWE BW1 BW2 GW CE1,CE2, CE3 OE ADV ADSP, ADSC DQ DQP MATCH MOE DE ZZ FT LBO TMS TDI TDO TCK VDD VSS VDDQ NC
Description
Address Input Signals--Inputs are registered and must meet setup and hold times, as specified on page 11. Clock Input Signal Byte Write Enable Signal--The byte write enable signal needs to be combined with one of the four byte write signals for a write operation to occur. Byte Write signal for data outputs 1 thru 8 Byte Write signal for data outputs 9 thru 16 Global Write Enable Chip Enables Output Enable Burst address advance Address status signals Data Input and Output pins Parity Input and Output pins Match Output Match Output Enable Data Enable--Data input registers are updated only when DE is active. Power down control--Application of ZZ will result in a low standby power consumption. Flow Through or Pipeline mode Linear Order Burst mode Test Mode Select Test Data In Test Data Out Test Clock 3.3 V power supply Ground 2.5 V/3.3 V output power supply No Connect
Rev: 1.03 4/2005
4/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
PBGA Pin Description Symbol
An CLK BWE BW1 BW2 GW CE1,CE2, CE3 OE ADV ADSP, ADSC DQ DQP MATCH MOE DE ZZ FT LBO TMS TDI TDO TCK VDD VSS VDDQ NC
Description
Address Input Signals--Inputs are registered and must meet setup and hold times, as specified on page 11. Clock Input Signal Byte Write Enable Signal--The byte write enable signal needs to be combined with one of the four byte write signals for a write operation to occur. Byte Write signal for data outputs 1 thru 8 Byte Write signal for data outputs 9 thru 16 Global Write Enable Chip Enables Output Enable Burst address advance Address status signals Data Input and Output pins Parity Input and Output pins Match Output Match Output Enable Data Enable--Data input registers are updated only when DE is active. Power down control--Application of ZZ will result in a low standby power consumption. Flow Through or Pipeline mode Linear Order Burst mode Test Mode Select Test Data In Test Data Out Test Clock 3.3 V power supply Ground 2.5 V/3.3 V output power supply No Connect
Rev: 1.03 4/2005
5/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Functional Block Diagram
18 A0-17
REGISTER
D
Q
A0 A1
A0 D0 D1 BINARY COUNTER Q0 Q1 A1 18 A
Load LBO ADV CLK ADSC ADSP Q
256K X 18
Memory Array
D
GW BWE BW1 Register D Q BW2 D D Q
Register Register Register
Register D Q
18 2
18
Q
Q
D
DE Register D Q
CE1 CE2 CE3 ZZ FT OE MOE A, DQ, Control Powerdown Control
Register D Q
Register D Q
18 54 Boundary Scan Registers Bypass Reg ID Reg. Instruction Reg. TDO DQ1-16 DQP1-2 Match
TDI
always (O)
TMS TCK
TAP Controller
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(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Mode Pin Function
LBO
L H or NC Power Down Control
Function
Linear Burst Interleaved Burst
FT
L H or NC
Function
Flow Through Pipeline
ZZ
L or NC H
Function
Active Standby, IDD = ISB
Note: There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
Byte Write Function Function
Read Read Write all bytes Write all bytes Write byte 1 Write byte 2 Note: H = logic high, L = logic low, NC = no connect
GW
H H L H H H
BWE
H L X L L L
BW1
X H X L L H
BW2
X H X L H L
Rev: 1.03 4/2005
7/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Synchronous Truth Table
Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used none none none none none external external external external external next next next next next next current current current current current current CE1 H L L L L L L L L L X X H H X H X X H H X H CE2 X L X L X H H H H H X X X X X X X X X X X X CE3 X X H X H L L L L L X X X X X X X X X X X X ADSP X L L H H L L H H H H H X X H X H H X X H X ADSC L X X L L X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X L L L L L L H H H H H H Write X X X X X X X H H L H H H H L L H H H H L L OE CLK X X X X X L H L H X L H L H X X L H L H X X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z Q High-Z Q High-Z D Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Notes: 1. X means "don't care," H means "logic high," L means "logic low." 2. 3. 4. 5. 6. Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail. All inputs, except OE, must meet setup and hold on rising edge of CLK. Suspending busrt generates a wait cycle. ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK). A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle. Refer to page 12 for the Write timing diagram.
Rev: 1.03 4/2005
8/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Truth Table For Read/Write/Compare/Fill Write Operation CE
Read Write Compare Fill Write Match Deselect Deselect L L L L H H
Write
H L H L X X
DE
X L L H X X
MOE
X X L X L H
OE
L H H X X X
Match
-- -- Data Out -- High High Z
DQ
Q D D X High Z High Z
Notes: 1. X means "don't care," H means "logic high," L means "logic low." 2. Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail. 3. CE is defined as CE1=L, CE2=H and CE3=L 4. All signals are synchronous and are sampled by CLK except OE and MOE. OE and MOE are asynchronous and drive the bus immediately.
)
Absolute Maximum Ratings (Voltage reference to VSS = 0 V) Symbol
VDD VDDQ VCLK Vin Vout Iout PD TOPR TSTG
Description
Supply Voltage Output Supply Voltage CLK Input Voltage Input Voltage Output Voltage Output Current per I/O Power Dissipation Operating Temperature Storage Temperature
Commerical
-0.5 to 4.6 -0.5 to VDD -0.5 to 6 -0.5 to VDD + 0.5 ( 4.6 V max. ) -0.5 to VDD + 0.5 ( 4.6 V max. ) +/-20 1.5 0 to 70 -55 to 125
Unit
V V V V V mA W
o o
C C
Note: Permanent damage to the device may occur if the Absolute Maximun Ratings are exceeded. Functional operation should be restricted to the recommended operation conditions. Exposure to higher than recommended voltages, for an extended period of time, could effect the performance and reliability of this component.
Rev: 1.03 4/2005
9/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Package Thermal Characteristics Rating
Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP)
Notes:
Layer Board
single four --
Symbol
RJA RJA RJC
TQFP max
32 20 7
PBGA max
28 18 4
Unit
C/W C/W C/W
Notes
1,2 1,2 3
1. 2. 3.
Junction temperature is a function of SRAM power dissapation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. SCMI G-38-87. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
AC Test Conditions (VDD = 3.135 V-3.6 V, Ta = 0-70C)
Output load 1 DQ
Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. 2. 3. 4. Include scope and jig capacitance.
Conditions
VIH = 2.3 V VIL = 0.2 V TR = 1 V/ns 1.25 V 1.25 V Fig. 1& 2 DQ 5pF1 FIG. 2 Output load 2 FIG. 1
50W VT = 1.25 V
30pF1
2.5 V 225W 225W
Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. Output load 2 for tLZ, tHZ, tOLZ and tOHZ. Device is deselected as defined by the Truth Table.
Rev: 1.03 4/2005
10/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
DC Characteristics and Supply Currents (Voltage reference to VSS = 0 V)
(VDD = 3.135 V-3.6 V, Ta = 0-70C for Commercial Temperature Offering)
Parameter
Input Leakage Current (except ZZ, FT, LBO pins) ZZ Input Current Mode Input Current (FT & LBO pins) Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage
Symbol
IIL IinZZ IinM Iol VOH VOH VOL
Test Conditions
VIN = 0 to VDD VDD VIN VIH 0 V VIN VIH VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDD IOH = -4 mA, VDDQ = 2.375 V IOH = -4 mA, VDDQ = 3.135 V IOL = +4 mA
Min
-1 uA -1 uA -1 uA -30 0uA -1 uA -1 uA 1.7 V 2.4 V
Max
1 uA 1 uA 300 uA 1 uA 1 uA 1 uA
0.4 V
Rev: 1.03 4/2005
11/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Operating Currents
-180 Parameter Test Conditions Symbol 0 to 70C 335 -40 to 85C 345 -166 -150 -133 -100 0 -40 0 -40 0 -40 0 -40 Unit to to to to to to to to 70C +85C 70C +85C 70C +85C 70C +85C 310 320 275 285 250 260 190 200 mA
Operating Current
Device Selected; All other inputs VIH Or VIL Output open
IDD Pipeline IDD Flow Through ISB Pipeline
210
220
190
200
190
200
140
150
140
150
mA
20
30
30
40
30
40
30
40
30
40
mA
Standby Current
ZZ VDD - 0.2 V
ISB Flow Through IDD Pipeline IDD Flow Through
20
30
30
40
30
40
30
40
30
40
mA
Deselect Supply Current
Device Deselected; All other inputs VIH OR VIL
55
65
110
120
105
115
100
110
80
90
mA
40
50
80
90
80
90
65
75
65
75
mA
Rev: 1.03 4/2005
12/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
AC Electrical Characteristics
Parameter
Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Clock to Match Valid Clock to Match Invalid Clock to Match in Low-Z Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to Output in Low-Z Clock to Match Valid Clock to Match Invalid Clock to Match in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z OE to Output Valid OE to output in Low-Z OE to output in High-Z MOE to Match Valid MOE to Match in Low-Z MOE to Match in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery
Symbol
tKC tKQ tKQX tLZ1 tKM tKMX tMLZ1 tKC tKQ tKQX tLZ1 tKM tKMX tMLZ1 tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tMOE tMOLZ1 tMOHZ1 tS tH tZZS2 tZZH2 tZZR
-180 Min
5.5 -- 1.5 1.5 -- 1.5 1.5 9.1 -- 3.0 3.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- -- 0 -- 1.5 0.5 5 1 20
-166 Min
6.0 -- 1.5 1.5 -- 1.5 1.5 10.0 -- 3.0 3.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- -- 0 -- 1.5 0.5 5 1 20
-150 Min
6.7 -- 1.5 1.5 -- 1.5 1.5 10.0 -- 3.0 3.0 -- 3.0 3.0 1.5 1.7 1.5 -- 0 -- -- 0 -- 1.5 0.5 5 1 20
-133 Min
7.5 -- 1.5 1.5 -- 1.5 1.5 15.0 -- 3.0 3.0 -- 3.0 3.0 1.7 1.9 1.5 -- 0 -- -- 0 -- 2.0 0.5 5 1 20
-100 Min
10 -- 1.5 1.5 -- 1.5 1.5 15.0 -- 3.0 3.0 -- 3.0 3.0 2 2.2 1.5 -- 0 -- -- 0 -- 2.0 0.5 5 1 20
Max
-- 3.2 -- -- 3.2 -- -- -- 8.0 -- -- 8.5 -- -- -- -- 3.2 3.2 -- 3.2 3.2 -- 3.2 -- -- -- -- --
Max
-- 3.5 -- -- 3.5 -- -- -- 8.5 -- -- 8.5 -- -- -- -- 3.5 3.5 -- 3.5 3.5 -- 3.5 -- -- -- -- --
Max
-- 3.8 -- -- 3.8 -- -- -- 10.0 -- -- 10.0 -- -- -- -- 3.8 3.8 -- 3.8 3.8 -- 3.8 -- -- -- -- --
Max
-- 4 -- -- 4 -- -- -- 11.0 -- -- 11.0 -- -- -- -- 4 4 -- 4 4 -- 4 -- -- -- -- --
Max
-- 4.5 -- -- 4.5 -- -- -- 12.0 -- -- 12.0 -- -- -- -- 5 5 -- 5 5 -- 5 -- -- -- -- --
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 1.03 4/2005
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(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Pipeline Mode Timing
Begin
Read A
Cont
Deselect Deselect Write B tKL tKH tKC
Read C
Read C+1 Read C+2 Read C+3 Cont
Deselect Deselect
CK ADSP tS tH ADSC tS ADV tS tH Ao-An
A B C ADSC initiated read
tH
tS GW tS BW tH tS Ba-Bd tS tH E1 tS tH E2 tS tH E3 G tS tOE DQa-DQd
Hi-Z E2 and E3 only sampled with ADSC Deselected with E1
tH
tKQ tH tLZ
Q(C) Q(C+1) Q(C+2) Q(C+3)
tHZ tKQX
tOHZ
Q(A) D(B)
Rev: 1.03 4/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Flow Through Mode Timing
Begin
Read A
Cont tKL tKH
Deselect Write B tKC
Read C
Read C+1 Read C+2 Read C+3 Read C
Deselect
CK ADSP tS tH ADSC tH tS ADV tS tH Ao-An
A B C Fixed High
tS tH ADSC initiated read
tS
tH
tS tH GW tS tH BW tH tS Ba-Bd tS tH E1 tS tH E2 tS tH E3 G tOE tKQ DQa-DQd
Q(A) E1 masks ADSP Deselected with E1
E2 and E3 only sampled with ADSP and ADSC
E1 masks ADSP
tH tS tOHZ
D(B)
tLZ
Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
tKQX tHZ
Rev: 1.03 4/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Pipeline Compare Fill Write Cycle
Hit
Miss
Fill Write
K tH tS Address A tH tS DQ A tH tS CE tH tS W G tH tS DE MOE tKM tMOE tMLZ Match A B B
tKM tKMX
tKM
Rev: 1.03 4/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Flow Through Compare Fill Write Cycle
Hit
Miss
Fill Write
K tH tS Address A tH tS DQ A tH tS CE tH tS W G tH tS DE MOE tKM tMOE tMLZ Match A B B
tKM tKMX
tKM
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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TQFP Package Drawing (Package T) Symbol
A1 A2 b c D D1 E E1 e L L1 Y
Description
Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle
Min. Nom. Max
0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 -- 0.45 -- 0 0.10 1.40 0.30 -- 22.0 20.0 16.0 14.0 0.65 0.60 1.00 -- 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 -- 0.75 -- 0.10 7
L L1
c Pin 1
e b
D D1
A1
Y
A2
E1 E
Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion.
Rev: 1.03 4/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Package Dimensions--119-Bump FPBGA (Package B, Variation 2)
A1 1
A B C D E F G H J K L M N P R T U
TOP VIEW
BOTTOM VIEW A1 O0.10S C O0.30S C AS B S O0.60~0.90 (119x)
2
3
4
5
6
7
7 6 5 43 2 1
A B C D E F G H J K L M N P R T U
220.10
B 0.700.05 0.15 C 1.27 7.62 0.15 C A 0.20(4x) 140.10
0.560.05
Rev: 1.03 4/2005
0.50~0.70 1.86.0.13
C
SEATING PLANE
19/21
20.32
1.27
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Ordering Information Org
256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18
Part Number1
GS841E18AT-180 GS841E18AT-166 GS841E18AT-150 GS841E18AT-133 GS841E18AT-100 GS841E18AT-180I GS841E18AT-166I GS841E18AT-150I GS841E18AT-133I GS841E18AT-100I GS841E18AGT-180 GS841E18AGT-166 GS841E18AGT-150 GS841E18AGT-133 GS841E18AGT-100 GS841E18AGT-180I GS841E18AGT-166I GS841E18AGT-150I GS841E18AGT-133I GS841E18AGT-100I GS841E18AB-180 GS841E18AB-166 GS841E18AB-150 GS841E18AB-133 GS841E18AB-100 GS841E18AB-180I GS841E18AB-166I GS841E18AB-150I GS841E18AI-133I
Type
DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through
Package
TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Pb-Free TQFP Pb-Free TQFP Pb-Free TQFP Pb-Free TQFP Pb-Free TQFP Pb-Free TQFP Pb-Free TQFP Pb-Free TQFP Pb-Free TQFP Pb-Free TQFP 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2)
Speed2 (MHz/ns)
180/8 166/8.5 150/10 133/11 100/12 180/8 166/8.5 150/10 133/11 100/12 180/8 166/8.5 150/10 133/11 100/12 180/8 166/8.5 150/10 133/11 100/12 180/8 166/8.5 150/10 133/11 100/12 180/8 166/8.5 150/10 133/11
TA
3
Status
C C C C C I I I I I C C C C C I I I I I C C C C C I I I I
256K x 18 GS841E18AB-100I DCD Pipeline/Flow Through 119 BGA (var. 2) 100/12 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS841E18AT-166T. 2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline / Flow through mode selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings. Rev: 1.03 4/2005 20/21 (c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
4Mb Synchronous Tag RAM Datasheet Revision History Rev. Code: Old;New
GS841E18A_r1 GS841E18A_r1; GS841E18A_r1_01 Content
Types of Changes Page /Revisions;Reason Format or Content
* Creation of new datasheet * Moved TCK from U6 (incorrect placement) to U4 (correct placement) on BGA * Changed U6 to NC * Updated format * Added 180 MHz speed bin * Updated timing diagrams * Updated mechanical drawings * Added Pb-Free info for TQFP * Added Pipeline Compare Fill Write Cycle and Flow Through Compare Fill Write Cycle timing diagrams
GS841E18A_r1_01; GS841E18A_r1_02 GS841E18A_r1_02; GS841E18A_r1_03
Format/Content
Content
Rev: 1.03 4/2005
21/21
(c) 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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